As an example of a non-volatile memory, a flash memory is known. In the flash memory, charge needs to be injected to a floating gate with high voltage and a step-up circuit is needed for writing and erasing data. The flash memory has a problem of high power consumption due to generation of high voltage with a step-up circuit.
Not only in the flash memory but also in other semiconductor memories, a memory cell array includes a defective memory cell in which data cannot be stored. Because data cannot be accurately stored when a defective memory cell is included, the method in which a defective memory cell is cut by a laser in a manufacturing step is used as the countermeasure, for example. An advantage of laser cut is that a manufacturing process does not need to be changed. However, a special apparatus is required because an inspection step is needed for performing the laser cut, which causes a problem in that the operation is complicated.
As another way to compensate a defective memory cell, there is a method in which a redundant memory cell array is provided in addition to a main memory cell array (e.g., see Patent Document 1). According to the method, address data of a defective memory cell in the main memory cell array is stored in the redundant data storage memory cell array, and in accordance with the stored data, when the defective memory cell is selected, the redundant memory cell is read out instead of the defective memory cell.
However, the redundant data storage memory cell array in which address data of a defective memory cell is stored includes memory cells which are the same as those of the main memory cell array; therefore, the memory capacity which the memory device should have had is reduced.
Further, the redundant data storage memory cell array is manufactured through the same process and includes a memory cell with the same structure as the main memory cell array, which means that a defective memory cell is generated as often as in the main memory cell array. Therefore, the redundant data storage memory cell array also needs an inspection step for finding a defective memory cell.
[Reference]
[Patent Document]
[Patent Document 1] Japanese Published Patent Application No. H11-232895